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Beijing E-Town enterprises release world's first RISC-V edge computing chip

Updated: 2024-04-10

Speaking of the recently released global first RISC-V edge computing chip (RISC-V is an open-source instruction set architecture), He Ning, senior vice president of Beijing ESWIN Computing Technology Co in Beijing E-Town, stated that, "The world's first RISC-V edge computing chip EIC7700, based on the RISC-V computing architecture, has achieved new 'evolution' in multiple indicators.”


Demonstration of the world's first RISC-V edge computing chip EIC7700 [Photo/beijingetown.com.cn]

The RISC-V chip has powerful video coding and decoding capabilities, supporting the decoding of 32 channels of 1080P30 frames and the encoding of 13 channels of 1080P30 frames, which can run in parallel with inference functions. 

The image signal processor (ISP) can provide various image processing hardware acceleration functions such as image enhancement, dynamic contrast enhancement, and distortion correction. It has rich multimedia input and output, PCIe (a high-speed serial computer expansion bus standard), Ethernet, and other external interfaces, He added.

To promote the landing of application scenarios on the edge side, EIC7700 also has three product forms: chips, PCIe cards, and AI edge intelligent stations, supporting AI high-precision large language models.

"In the past two years, RISC-V has begun to land in strong ecological scenes such as edge computing. The main challenge lies in the ecosystem, including compatibility and integration with existing technology stacks, operating systems, development tools, etc., and the porting of applications running on the original architecture," he said. 

Rooted in the innovative soil of Beijing E-Town, ESWIN will strengthen the research and development of RISC-V architecture, the landing of products, and the promotion of ecology, especially in the field of intelligent computing, fully leveraging the advantages of RISC-V architecture, deeply integrating with AI, and building a new ecosystem of "RISC-V + AI".